/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
 */
#ifndef _ASM_IO_H
#define _ASM_IO_H

#include <linux/kernel.h>
#include <linux/types.h>

#include <asm/addrspace.h>
#include <asm/cpu.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
#include <asm/string.h>

/*
 * Change "struct page" to physical address.
 */
#define page_to_phys(page)	((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)

extern void __init __iomem *early_ioremap(u64 phys_addr, unsigned long size);
extern void __init early_iounmap(void __iomem *addr, unsigned long size);

#define early_memremap early_ioremap
#define early_memunmap early_iounmap

#ifdef CONFIG_ARCH_IOREMAP

static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
					 unsigned long prot_val)
{
	switch (prot_val & _CACHE_MASK) {
	case _CACHE_CC:
		return (void __iomem *)(unsigned long)(CACHE_BASE + offset);
	case _CACHE_SUC:
		return (void __iomem *)(unsigned long)(UNCACHE_BASE + offset);
	case _CACHE_WUC:
		return (void __iomem *)(unsigned long)(WRITECOMBINE_BASE + offset);
	default:
		return NULL;
	}
}

#define ioremap(offset, size)		\
	ioremap_prot((offset), (size), pgprot_val(PAGE_KERNEL_SUC))

#define iounmap(addr) 			((void)(addr))

#endif

/*
 * On LoongArch, ioremap() has two variants, ioremap_wc() and ioremap_cache().
 * They map bus memory into CPU space, the mapped memory is marked uncachable
 * (_CACHE_SUC), uncachable but accelerated by write-combine (_CACHE_WUC) and
 * cachable (_CACHE_CC) respectively for CPU access.
 *
 * @offset:    bus address of the memory
 * @size:      size of the resource to map
 */
#define ioremap_wc(offset, size)	\
	ioremap_prot((offset), (size),	\
		pgprot_val(wc_enabled ? PAGE_KERNEL_WUC : PAGE_KERNEL_SUC))

#define ioremap_cache(offset, size)	\
	ioremap_prot((offset), (size), pgprot_val(PAGE_KERNEL))

#define mmiowb() wmb()

/*
 * String version of I/O memory access operations.
 */
extern void __memset_io(volatile void __iomem *dst, int c, size_t count);
extern void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count);
extern void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count);
#define memset_io(c, v, l)     __memset_io((c), (v), (l))
#define memcpy_fromio(a, c, l) __memcpy_fromio((a), (c), (l))
#define memcpy_toio(c, a, l)   __memcpy_toio((c), (a), (l))

#define __io_aw() mmiowb()

#include <linux/spinlock.h>
extern spinlock_t lcl_node_lock[16];
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;
	u8 val;

	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node + 8], irq_flag);
	val = *(const volatile u8 __force *)addr;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node + 8], irq_flag);
	/* read barrier */
	rmb();
	return val;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;
	u16 val;

	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node + 8], irq_flag);
	val = *(const volatile u16 __force *)addr;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node + 8], irq_flag);
	/* read barrier */
	rmb();
	return val;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;
	u32 val;

	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node + 8], irq_flag);
	val = *(const volatile u32 __force *)addr;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node + 8], irq_flag);
	/* read barrier */
	rmb();
	return val;
}

#ifdef CONFIG_64BIT
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;
	u64 val;

	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node + 8], irq_flag);
	val = *(const volatile u64 __force *)addr;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node + 8], irq_flag);
	/* read barrier */
	rmb();
	return val;
}
#endif /* CONFIG_64BIT */

#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;

	/* write barrier */
	wmb();
	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node], irq_flag);
	*(volatile u8 __force *)addr = value;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node], irq_flag);
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 value, volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;

	/* write barrier */
	wmb();
	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node], irq_flag);
	*(volatile u16 __force *)addr = value;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node], irq_flag);
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 value, volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;

	/* write barrier */
	wmb();
	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node], irq_flag);
	*(volatile u32 __force *)addr = value;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node], irq_flag);
}

#ifdef CONFIG_64BIT
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
{
	unsigned long dst_node, node;
	unsigned long irq_flag;

	/* write barrier */
	wmb();
	dst_node = ((unsigned long)addr >> 44) & 0xf;
	node = get_csr_cpuid() / 32;
	if (node != dst_node)
		spin_lock_irqsave(&lcl_node_lock[node], irq_flag);
	*(volatile u64 __force *)addr = value;
	if (node != dst_node)
		spin_unlock_irqrestore(&lcl_node_lock[node], irq_flag);
}
#endif /* CONFIG_64BIT */
#include <asm-generic/io.h>

#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

#endif /* _ASM_IO_H */
